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| C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 80C166W/83C166W / 83C166W SAB 80C166W/ 83C166W/ 83C166W 16-Bit Microcontroller q q q q q q q q q q q q q q q q q q q q q q q q q q q High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bits), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip ROM (SAB 83C166W only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 s Conversion Time 16-Channel Capture/Compare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose I/O Lines Direct clock input without prescaler Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic MQFP Package (EIAJ) Semiconductor Group 1 10.94 SAB 80C166W/83C166W Introduction The SAB 80C166W/83C166W is a representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. These devices derive the CPU clock signal (operating clock) directly from the on-chip oscillator without using a prescaler. This reduces the device's EME. SAB 80C166W Figure 1 Logic Symbol Ordering Information Type SAB 83C166W-5M SAB 83C166W-5MT3 SAB 83C166W-5MT4 SAB 80C166W/ 83C166W-M Ordering Code Package On Request Q67120-D... Q67120-D... On Request Function P-MQFP-100-2 16-bit microcontroller, 0 C to +70 C, 1 KByte RAM and 32 KByte ROM P-MQFP-100-2 16-bit microcontroller, -40 C to +85 C, 1 KByte RAM and 32 KByte ROM P-MQFP-100-2 16-bit microcontroller, -40 C to +110 C 1 KByte RAM and 32 KByte ROM P-MQFP-100-2 16-bit microcontroller, 0 C to +70 C 1 KByte RAM Semiconductor Group 2 SAB 80C166W/83C166W Type SAB 80C166W/ 83C166W-M-T3 SAB 80C166W/ 83C166W-M-T4 Ordering Code Package Q67120-C864 Q67120-C917 Function P-MQFP-100-2 16-bit microcontroller, -40 C to +85 C 1 KByte RAM P-MQFP-100-2 16-bit microcontroller, -40 C to +110 C 1 KByte RAM Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration Rectangular P-MQFP-100-2 (top view) SAB 80C166W/ Figure 2 Semiconductor Group 3 SAB 80C166W/83C166W Pin Definitions and Functions Pin No. 16 - 17 Symbol P4.0 - P4.1 Input (I) Function Output (O) I/O Port 4 is a 2-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.1 A17 Most Significant Segment Addr. Line Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. External Bus Configuration selection inputs. These pins are sampled during reset and select either the single chip mode or one of the four external bus configurations: BUSACT EBC1 EBC0 Mode/Bus Configuration 0 0 0 8-bit demultiplexed bus 0 0 1 8-bit multiplexed bus 0 1 0 16-bit muliplexed bus 0 1 1 16-bit demultiplexed bus 1 0 0 Single chip mode 1 0 1 Reserved. 1 1 0 Reserved. 1 1 1 Reserved. ROMless versions must have pin BUSACT tied to `0'. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the SAB 80C166W/83C166W. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. XTAL1: 16 17 20 19 XTAL1 XTAL2 O O I O 22 23 24 BUSACT, I EBC1, I EBC0 I 27 RSTIN I 28 RSTOUT O Semiconductor Group 4 SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin No. 29 Symbol NMI Input (I) Function Output (O) I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the SAB 80C166W/83C166W to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pull NMI high externally. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Memory Read Strobe. RD is activated for every external instruction or data read access. Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.. Port 5 is a 10-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 10) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x). Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out ... ... ... P2.13 CC13IO CAPCOM: CC13 Cap.-In/Comp.Out, BREQ External Bus Request Output P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out, HLDA External Bus Hold Acknowl. Output P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, HOLD External Bus Hold Request Input 29 ALE O 26 30 - 37 40 - 47 RD P1.0 - P1.15 O I/O 48 - 53 56 - 59 P5.0 - P5.9 I I 62 - 77 P2.0 - P2.15 I/O 62 75 76 77 I/O I/O O I/O O I/O I Semiconductor Group 5 SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin No. Symbol Input (I) Function Output (O) I/O I/O Port 3 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 TxD1 ASC1 Clock/Data Output (Asyn./Syn.) P3.9 RxD1 ASC1 Data Input (Asyn.) or I/O (Syn.) P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, P3.13 WR External Memory Write Strobe P3.14 READY Ready Signal Input P3.15 CLKOUT System Clock Output (=CPU Clock) Port 0 is a 16-bit bidirectional IO port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 - P0.7: D0 - D7 D0 - D7 P0.8 - P0.15: output! D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 - P0.7: AD0 - AD7 AD0 - AD7 P0.8 - P0.15: A8 - A15 AD8 - AD15 Reference voltage for the A/D converter. Reference ground for the A/D converter. 80 - 92, P3.0 - 95 - 97 P3.15 80 81 82 83 84 85 86 87 88 89 90 91 92 95 96 97 98 - 5 8 - 15 P0.0 - P0.15 I O I O I I I I O I/O O I/O O O I O I/O 54 55 VAREF VAGND - Semiconductor Group 6 SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin No. 7, 18, 38, 61, 79, 93 6, 21, 39, 60, 78, 94 Symbol Input (I) Function Output (O) Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground. VCC VSS - Semiconductor Group 7 SAB 80C166W/83C166W Functional Description The architecture of the SAB 80C166W/83C166W combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the SAB 80C166W/83C166W. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram Semiconductor Group 8 SAB 80C166W/83C166W Memory Organization The memory space of the SAB 80C166W/83C166W is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address space expansion to 16 MBytes is provided for future versions. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The SAB 83C166W contains 32 KBytes of on-chip mask-programmable ROM for code or constant data. The ROM can be mapped to either segment 0 or segment 1. 1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register area. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the SAB 80C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 KBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - 16-/18-bit Addresses, 16-bit Data, Demultiplexed - 16-/18-bit Addresses, 16-bit Data, Multiplexed - 16-/18-bit Addresses, 8-bit Data, Multiplexed - 16-/18-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on Port 1 and data is input/output on Port 0. In the multiplexed bus modes both addresses and data use Port 0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory TriState Time, Read/Write Delay and Length of ALE, ie. address setup/hold time with respect to ALE) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Access to very slow memories is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 64 KBytes of external memory space, a non-segmented memory model can be selected. In this case all memory locations can be addressed by 16 bits and Port 4 is not required to output the additional segment address lines. Semiconductor Group 9 SAB 80C166W/83C166W Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the SAB 80C166W/83C166W's instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register banks may overlap others. 32 KByte in the SAB 83C166W 1 KByte Figure 4 CPU Block Diagram Semiconductor Group 10 SAB 80C166W/83C166W A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient SAB 80C166W/83C166W instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 11 SAB 80C166W/83C166W Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the SAB 80C166W/83C166W is capable of reacting very fast to the occurence of non-deterministic events. The architecture of the SAB 80C166W/83C166W supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The SAB 80C166W/83C166W has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible SAB 80C166W/83C166W interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Semiconductor Group 12 SAB 80C166W/83C166W Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Timer 0 CAPCOM Timer 1 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Overrun Error ASC0 Transmit ASC0 Receive ASC0 Error ASC1 Transmit ASC1 Receive ASC1 Error Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T0IR T1IR T2IR T3IR T4IR T5IR T6IR CRIR ADEIR S0TIR S0RIR S0EIR S1TIR S1RIR S1EIR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T0IE T1IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0RIE S0EIE S1TIE S1RIE S1EIE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T0INT T1INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0RINT S0EINT S1TINT S1RINT S1EINT Vector Location 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 80H 84H 88H 8CH 90H 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H BCH Trap Number 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH A/D Conversion Complete ADCIR Semiconductor Group 13 SAB 80C166W/83C166W The SAB 80C166W/83C166W also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET Vector Location 0000H 0000H 0000H Trap Number 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH [0BH - 0FH] Any [00H - 7FH] Current CPU Priority Trap Priority III III III II II II I I I I I NMITRAP 0008H STOTRAP 0010H STUTRAP 0018H BTRAP BTRAP BTRAP BTRAP BTRAP 0028H 0028H 0028H 0028H 0028H [002CH - 003CH] Any [0000H - 01FCH] in steps of 04H Semiconductor Group 14 SAB 80C166W/83C166W Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 400 ns (@ 20 MHz CPU clock). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/ compare register array. The input clock for the timers is programmable to several prescaled values of the CPU clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, an external count input for CAPCOM timer T0 allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Semiconductor Group 15 SAB 80C166W/83C166W x=0 y=1 Figure 5 CAPCOM-Unit Block Diagram Semiconductor Group 16 SAB 80C166W/83C166W General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20 MHz CPU clock). Figure 6 Block Diagram of GPT1 Semiconductor Group 17 SAB 80C166W/83C166W The count direction (up/down) for each timer is programmable by software. For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate e. g. position tracking. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/ underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for timeout monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Figure 7 Block Diagram of GPT2 Semiconductor Group 18 SAB 80C166W/83C166W With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. A/D Converter For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time adds up to 9.7 us @ 20 MHz CPU clock. Overrun error detection/protection is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the SAB 80C166W/83C166W supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Semiconductor Group 19 SAB 80C166W/83C166W Parallel Ports The SAB 80C166W/83C166W provides up to 76 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. Port 0 and Port 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A17/A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA, HOLD). Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE, READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with identical functionality, Asynchronous/ Synchronous Serial Channels ASC0 and ASC1. They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 Kbaud and half-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode one data byte is transmitted or received synchronously to a shift clock which is generated by the SAB 80C166W/83C166W. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Semiconductor Group 20 SAB 80C166W/83C166W Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 s and 420 ms can be monitored (@ 20 MHz CPU clock). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz CPU clock). Bootstrap Loader The SAB 80C166W/83C166W provides a built-in bootstrap loader (BSL), which allows to start program execution out of the SAB 80C166W/83C166W's internal RAM. This start program is loaded via the serial interface ASC0 and does not require external memory or an internal ROM. The SAB 80C166W/83C166W enters BSL mode, when ALE is sampled high at the end of a hardware reset and if NMI becomes active directly after the end of the internal reset sequence. BSL mode is entered independent of the bus mode selected via EBC0, EBC1 and BUSACT. After entering BSL mode the SAB 80C166W/83C166W scans the RXD0 line to receive a zero byte, ie. one start bit, eight `0' data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock and initializes ASC0 accordingly. Using this baudrate, an acknowledge byte is returned to the host that provides the loaded data. The SAB 80C166W/83C166W returns the value <55H>. The next 32 bytes received via ASC0 are stored sequentially into locations 0FA40H through 0FA5FH of the internal RAM. To execute the loaded code the BSL then jumps to location 0FA40H. The loaded program may load additional code / data, change modes, etc. The SAB 80C166W/83C166W exits BSL mode upon a software reset (ignores the ALE level) or a hardware reset (remove conditions for entering BSL mode before). Instruction Set Summary The summary on the following pages lists the instructions of the SAB 80C166W/83C166W ordered into logical groups. Semiconductor Group 21 SAB 80C166W/83C166W Instruction Set Summary Mnemonic Arithmetic Operations ADD ADD ADD ADD ADD ADD ADD ADDB ADDB ADDB ADDB ADDB ADDB ADDB ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDCB ADDCB ADDCB ADDCB ADDCB ADDCB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem Add direct word GPR to direct GPR Add indirect word memory to direct GPR Add indirect word memory to direct GPR and postincrement source pointer by 2 Add immediate word data to direct GPR Add immediate word data to direct register Add direct word memory to direct register Add direct word register to direct memory Add direct byte GPR to direct GPR Add indirect byte memory to direct GPR Add indirect byte memory to direct GPR and post-increment source pointer by 1 Add immediate byte data to direct GPR Add immediate byte data to direct register Add direct byte memory to direct register Add direct byte register to direct memory Add direct word GPR to direct GPR with Carry Add indirect word memory to direct GPR with Carry Add indirect word memory to direct GPR with Carry and post-increment source pointer by 2 Add immediate word data to direct GPR with Carry Add immediate word data to direct register with Carry Add direct word memory to direct register with Carry Add direct word register to direct memory with Carry Add direct byte GPR to direct GPR with Carry Add indirect byte memory to direct GPR with Carry Add indirect byte memory to direct GPR with Carry and post-increment source pointer by 1 Add immediate byte data to direct GPR with Carry Add immediate byte data to direct register with Carry Add direct byte memory to direct register with Carry 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 Description Bytes Semiconductor Group 22 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Arithmetic Operations (cont'd) ADDCB SUB SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBC SUBC SUBC SUBC SUBC SUBC SUBC SUBCB SUBCB SUBCB SUBCB SUBCB mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 Add direct byte register to direct memory with Carry Subtract direct word GPR from direct GPR Subtract indirect word memory from direct GPR Subtract indirect word memory from direct GPR and post-increment source pointer by 2 Subtract immediate word data from direct GPR Subtract immediate word data from direct register Subtract direct word memory from direct register Subtract direct word register from direct memory Subtract direct byte GPR from direct GPR Subtract indirect byte memory from direct GPR Subtract indirect byte memory from direct GPR and post-increment source pointer by 1 Subtract immediate byte data from direct GPR Subtract immediate byte data from direct register Subtract direct byte memory from direct register Subtract direct byte register from direct memory Subtract direct word GPR from direct GPR with Carry Subtract indirect word memory from direct GPR with Carry Subtract indirect word memory from direct GPR with Carry and post-increment source pointer by 2 Subtract immediate word data from direct GPR with Carry Subtract immediate word data from direct register with Carry 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 Subtract direct word memory from direct register with Carry 4 Subtract direct word register from direct memory with Carry 4 Subtract direct byte GPR from direct GPR with Carry Subtract indirect byte memory from direct GPR with Carry Subtract indirect byte memory from direct GPR with Carry and post-increment source pointer by 1 Subtract immediate byte data from direct GPR with Carry 2 2 2 2 Subtract immediate byte data from direct register with Carry 4 Semiconductor Group 23 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Arithmetic Operations (cont'd) SUBCB SUBCB MUL MULU DIV DIVL DIVLU DIVU CPL CPLB NEG NEGB reg, mem mem, reg Rw, Rw Rw, Rw Rw Rw Rw Rw Rw Rb Rw Rb Subtract direct byte memory from direct register with Carry Subtract direct byte register from direct memory with Carry Signed multiply direct GPR by direct GPR (16-16-bit) Unsigned multiply direct GPR by direct GPR (16-16-bit) Signed divide register MDL by direct GPR (16-/16-bit) Signed long divide register MD by direct GPR (32-/16-bit) Unsigned long divide register MD by direct GPR (32-/16-bit) Unsigned divide register MDL by direct GPR (16-/16-bit) Complement direct word GPR Complement direct byte GPR Negate direct word GPR Negate direct byte GPR 4 4 2 2 2 2 2 2 2 2 2 2 Logical Instructions AND AND AND AND AND AND AND ANDB ANDB ANDB ANDB ANDB ANDB ANDB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Bitwise AND direct word GPR with direct GPR Bitwise AND indirect word memory with direct GPR Bitwise AND indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise AND immediate word data with direct GPR Bitwise AND immediate word data with direct register Bitwise AND direct word memory with direct register Bitwise AND direct word register with direct memory Bitwise AND direct byte GPR with direct GPR Bitwise AND indirect byte memory with direct GPR Bitwise AND indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise AND immediate byte data with direct GPR Bitwise AND immediate byte data with direct register Bitwise AND direct byte memory with direct register Bitwise AND direct byte register with direct memory 2 2 2 2 4 4 4 2 2 2 2 4 4 4 Semiconductor Group 24 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Logical Instructions (cont'd) OR OR OR OR OR OR OR ORB ORB ORB ORB ORB ORB ORB XOR XOR XOR XOR XOR XOR XOR XORB XORB XORB XORB XORB XORB XORB Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem mem, reg Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem mem, reg Bitwise OR direct word GPR with direct GPR Bitwise OR indirect word memory with direct GPR Bitwise OR indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise OR immediate word data with direct GPR Bitwise OR immediate word data with direct register Bitwise OR direct word memory with direct register Bitwise OR direct word register with direct memory Bitwise OR direct byte GPR with direct GPR Bitwise OR indirect byte memory with direct GPR Bitwise OR indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise OR immediate byte data with direct GPR Bitwise OR immediate byte data with direct register Bitwise OR direct byte memory with direct register Bitwise OR direct byte register with direct memory Bitwise XOR direct word GPR with direct GPR Bitwise XOR indirect word memory with direct GPR Bitwise XOR indirect word memory with direct GPR and post-increment source pointer by 2 Bitwise XOR immediate word data with direct GPR Bitwise XOR immediate word data with direct register Bitwise XOR direct word memory with direct register Bitwise XOR direct word register with direct memory Bitwise XOR direct byte GPR with direct GPR Bitwise XOR indirect byte memory with direct GPR Bitwise XOR indirect byte memory with direct GPR and post-increment source pointer by 1 Bitwise XOR immediate byte data with direct GPR Bitwise XOR immediate byte data with direct register Bitwise XOR direct byte memory with direct register Bitwise XOR direct byte register with direct memory 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 2 2 2 2 4 4 4 Semiconductor Group 25 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR BSET BMOV BMOVN BAND BOR BXOR BCMP BFLDH BFLDL CMP CMP CMP CMP CMP CMP CMPB CMPB CMPB CMPB CMPB CMPB bitaddr bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitaddr, bitaddr bitoff, #mask8, #data8 bitoff, #mask8, #data8 Rw, Rw Rw, [Rw] Rw, [Rw +] Rw, #data3 reg, #data16 reg, mem Rb, Rb Rb, [Rw] Rb, [Rw +] Rb, #data3 reg, #data8 reg, mem Clear direct bit Set direct bit Move direct bit to direct bit Move negated direct bit to direct bit AND direct bit with direct bit OR direct bit with direct bit XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high byte of bit-addressable direct word memory with immediate data Bitwise modify masked low byte of bit-addressable direct word memory with immediate data Compare direct word GPR to direct GPR Compare indirect word memory to direct GPR Compare indirect word memory to direct GPR and post-increment source pointer by 2 Compare immediate word data to direct GPR Compare immediate word data to direct register Compare direct word memory to direct register Compare direct byte GPR to direct GPR Compare indirect byte memory to direct GPR Compare indirect byte memory to direct GPR and post-increment source pointer by 1 Compare immediate byte data to direct GPR Compare immediate byte data to direct register Compare direct byte memory to direct register 2 2 4 4 4 4 4 4 4 4 2 2 2 2 4 4 2 2 2 2 4 4 Compare and Loop Control Instructions CMPD1 CMPD1 Rw, #data4 Rw, #data16 Compare immediate word data to direct GPR and decrement GPR by 1 Compare immediate word data to direct GPR and decrement GPR by 1 2 4 Semiconductor Group 26 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Compare and Loop Control Instructions (cont'd) CMPD1 CMPD2 CMPD2 CMPD2 CMPI1 CMPI1 CMPI1 CMPI2 CMPI2 CMPI2 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Rw, #data4 Rw, #data16 Rw, mem Compare direct word memory to direct GPR and decrement GPR by 1 Compare immediate word data to direct GPR and decrement GPR by 2 Compare immediate word data to direct GPR and decrement GPR by 2 Compare direct word memory to direct GPR and decrement GPR by 2 Compare immediate word data to direct GPR and increment GPR by 1 Compare immediate word data to direct GPR and increment GPR by 1 Compare direct word memory to direct GPR and increment GPR by 1 Compare immediate word data to direct GPR and increment GPR by 2 Compare immediate word data to direct GPR and increment GPR by 2 Compare direct word memory to direct GPR and increment GPR by 2 4 2 4 4 2 4 4 2 4 4 Prioritize Instruction PRIOR Rw, Rw Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR 2 Shift and Rotate Instructions SHL SHL SHR Rw, Rw Rw, #data4 Rw, Rw Shift left direct word GPR; number of shift cycles specified by direct GPR Shift left direct word GPR; number of shift cycles specified by immediate data Shift right direct word GPR; number of shift cycles specified by direct GPR 2 2 2 Semiconductor Group 27 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description Bytes Shift and Rotate Instructions (cont'd) SHR ROL ROL ROR ROR ASHR ASHR Rw, #data4 Rw, Rw Rw, #data4 Rw, Rw Rw, #data4 Rw, Rw Rw, #data4 Shift right direct word GPR; number of shift cycles specified by immediate data Rotate left direct word GPR; number of shift cycles specified by direct GPR Rotate left direct word GPR; number of shift cycles specified by immediate data Rotate right direct word GPR; number of shift cycles specified by direct GPR Rotate right direct word GPR; number of shift cycles specified by immediate data Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by direct GPR Arithmetic (sign bit) shift right direct word GPR; number of shift cycles specified by immediate data 2 2 2 2 2 2 2 Data Movement MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Rw, Rw Rw, #data4 reg, #data16 Rw, [Rw] Rw, [Rw+] [Rw], Rw [-Rw], Rw [Rw], [Rw] [Rw+], [Rw] [Rw], [Rw+] Rw, [Rw + #data16] Move direct word GPR to direct GPR Move immediate word data to direct GPR Move immediate word data to direct register Move indirect word memory to direct GPR Move indirect word memory to direct GPR and post-increment source pointer by 2 Move direct word GPR to indirect memory Pre-decrement destination pointer by 2 and move direct word GPR to indirect memory Move indirect word memory to indirect memory Move indirect word memory to indirect memory and post-increment destination pointer by 2 Move indirect word memory to indirect memory and post-increment source pointer by 2 Move indirect word memory by base plus constant to direct GPR 2 2 4 2 2 2 2 2 2 2 4 4 [Rw + #data16], Move direct word GPR to indirect memory by base plus Rw constant Semiconductor Group 28 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Data Movement (cont'd) MOV MOV MOV MOV MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVBS MOVBS MOVBS [Rw], mem mem, [Rw] reg, mem mem, reg Rb, Rb Rb, #data4 reg, #data8 Rb, [Rw] Rb, [Rw +] [Rw], Rb [-Rw], Rb [Rw], [Rw] [Rw +], [Rw] [Rw], [Rw +] Rb, [Rw + #data16] Move direct word memory to indirect memory Move indirect word memory to direct memory Move direct word memory to direct register Move direct word register to direct memory Move direct byte GPR to direct GPR Move immediate byte data to direct GPR Move immediate byte data to direct register Move indirect byte memory to direct GPR Move indirect byte memory to direct GPR and post-increment source pointer by 1 Move direct byte GPR to indirect memory Pre-decrement destination pointer by 1 and move direct byte GPR to indirect memory Move indirect byte memory to indirect memory Move indirect byte memory to indirect memory and post-increment destination pointer by 1 Move indirect byte memory to indirect memory and post-increment source pointer by 1 Move indirect byte memory by base plus constant to direct GPR 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 4 4 Description Bytes [Rw + #data16], Move direct byte GPR to indirect memory by base plus Rb constant [Rw], mem mem, [Rw] reg, mem mem, reg Rw, Rb reg, mem mem, reg Move direct byte memory to indirect memory Move indirect byte memory to direct memory Move direct byte memory to direct register Move direct byte register to direct memory Move direct byte GPR with sign extension to direct word GPR Move direct byte memory with sign extension to direct word register Move direct byte register with sign extension to direct word memory Semiconductor Group 29 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Data Movement (cont'd) MOVBZ MOVBZ MOVBZ Rw, Rb reg, mem mem, reg Move direct byte GPR with zero extension to direct word GPR Move direct byte memory with zero extension to direct word register Move direct byte register with zero extension to direct word memory 2 4 4 Description Bytes Jump and Call Operations JMPA JMPI JMPR JMPS JB JBC JNB JNBS CALLA CALLI CALLR CALLS PCALL TRAP cc, caddr cc, [Rw] cc, rel seg, caddr bitaddr, rel bitaddr, rel bitaddr, rel bitaddr, rel cc, caddr cc, [Rw] rel seg, caddr reg, caddr #trap7 Jump absolute if condition is met Jump indirect if condition is met Jump relative if condition is met Jump absolute to a code segment Jump relative if direct bit is set Jump relative and clear bit if direct bit is set Jump relative if direct bit is not set Jump relative and set bit if direct bit is not set Call absolute subroutine if condition is met Call indirect subroutine if condition is met Call relative subroutine Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number 4 2 2 4 4 4 4 4 4 2 2 4 4 2 System Stack Operations POP PUSH SCXT SCXT reg reg reg, #data16 reg, mem Pop direct word register from system stack Push direct word register onto system stack Push direct word register onto system stack und update register with immediate data Push direct word register onto system stack und update register with direct memory 2 2 4 4 Semiconductor Group 30 SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Return Operations RET RETS RETP RETI System Control SRST IDLE PWRDN SRVWDT DISWDT EINIT Miscellaneous NOP Null operation 2 Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin 4 4 4 4 4 4 reg Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine 2 2 2 2 Description Bytes Semiconductor Group 31 SAB 80C166W/83C166W Instruction Set Summary Notes Data Addressing Modes Rw: Rb: reg: mem: [...]: - Word GPR (R0, R1, ... , R15) - Byte GPR (RL0, RH0, ..., RL7, RH7) - SFR or GPR (in case of a byte operation on an SFR, only the low byte can be accessed via `reg') - Direct word or byte memory location - Indirect word or byte memory location (Any word GPR can be used as indirect address pointer, except for the arithmetic, logical and compare instructions, where only R0 to R3 are allowed) - Direct bit in the bit-addressable memory area - Direct word in the bit-addressable memory area - Immediate constant (The number of significant bits which can be specified by the user is represented by the respective appendix 'x') - Immediate 8-bit mask used for bit-field modifications bitaddr: bitoff: #data: #mask8: Multiply and Divide Operations The MDL and MDH registers are implicit source and/or destination operands of the multiply and divide instructions. Branch Target Addressing Modes caddr: seg: rel: #trap7: - Direct 16-bit jump target address (Updates the Instruction Pointer) - Direct 2-bit segment address (Updates the Code Segment Pointer) - Signed 8-bit jump target word offset address relative to the Instruction Pointer of the following instruction - Immediate 7-bit trap or interrupt number. Semiconductor Group 32 SAB 80C166W/83C166W Branch Condition Codes cc: Symbolically specifiable condition codes cc_UC cc_Z cc_NZ cc_V cc_NV cc_N cc_NN cc_C cc_NC cc_EQ cc_NE cc_ULT cc_ULE cc_UGE cc_UGT cc_SLE cc_SGE cc_SGT cc_NET - - - - - - - - - - - - - - - - - - - Unconditional Zero Not Zero Overflow No Overflow Negative Not Negative Carry No Carry Equal Not Equal Unsigned Less Than Unsigned Less Than or Equal Unsigned Greater Than or Equal Unsigned Greater Than Signed Less Than or Equal Signed Greater Than or Equal Signed Greater Than Not Equal and Not End-of-Table Instruction Op Codes in Hexadecimal Order The table on the following pages lists the SAB 80C166W/83C166W's instruction opcodes in a hexadecimal order. This table allows to find the instruction which is associated with a given opcode. Semiconductor Group 33 SAB 80C166W/83C166W Hexcode 00 01 02 03 04 05 06 07 08 Num- Mnemonic ber of Bytes 2 2 4 4 4 4 4 4 2 ADD ADDB ADD ADDB ADD ADDB ADD ADDB ADD Operands Hexcode 19 Num- Mnemonic ber of Bytes 2 ADDCB Operands Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, Rw cc_UC, rel bitoff.0 bitoff.0 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitoff, #mask8, #data8 Rw, Rw Rw, #data4 cc_NET, rel bitoff.1 bitoff.1 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data6 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw, Rw Rw, Rw cc_EQ, rel or cc_Z, rel bitoff.2 bitoff.2 Rw, Rw Rb, Rb reg, mem 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 BFLDH MULU ROL JMPR BCLR BSET SUB SUBB SUB SUBB SUB SUBB SUB SUBB SUB 09 2 ADDB 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 BFLDL MUL ROL JMPR BCLR BSET ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC ADDCB ADDC 29 2 SUBB 2A 2B 2C 2D 2E 2F 30 31 32 4 2 2 2 2 2 2 2 4 BCMP PRIOR ROR JMPR BCLR BSET SUBC SUBCB SUBC Semiconductor Group 34 SAB 80C166W/83C166W Hexcode 33 34 35 36 37 38 Num- Mnemonic ber of Bytes 4 4 4 4 4 2 SUBCB SUBC SUBCB SUBC SUBCB SUBC Operands Hexcode 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 Num- Mnemonic ber of Bytes 2 2 2 2 2 2 4 4 4 4 4 4 2 SHL JMPR BCLR BSET XOR XORB XOR XORB XOR XORB XOR XORB XOR Operands reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw, #data4 cc_NE, rel or cc_NZ, rel bitoff.3 bitoff.3 Rw, Rw Rb, Rb reg, mem reg, mem reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, Rw cc_V, rel bitoff.4 bitoff.4 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, #data4 cc_NV, rel bitoff.5 bitoff.5 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 39 2 SUBCB 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 4 2 2 2 2 2 2 4 4 4 4 2 BMOVN ROR JMPR BCLR BSET CMP CMPB CMP CMPB CMP CMPB CMP 59 2 XORB 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 4 2 2 2 2 2 2 2 4 4 4 4 4 4 BOR DIVU SHL JMPR BCLR BSET AND ANDB AND ANDB AND ANDB AND ANDB 49 2 CMPB 4A 4B 4 2 BMOV DIV Semiconductor Group 35 SAB 80C166W/83C166W Hexcode 68 Num- Mnemonic ber of Bytes 2 AND Operands Hexcode 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 Num- Mnemonic ber of Bytes 4 4 4 4 2 2 4 2 2 2 2 2 4 4 4 4 2 2 4 2 2 2 2 2 2 CMPI1 MOV CMPI1 IDLE MOV MOVB JB JMPR BCLR BSET CMPI2 CPL CMPI2 MOV CMPI2 PWRDN MOV MOVB JNB TRAP JMPI JMPR BCLR BSET CMPD1 Operands Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, Rw cc_N, rel bitoff.6 bitoff.6 Rw, Rw Rb, Rb reg, mem reg, mem mem, reg mem, reg reg, #data16 reg, #data8 Rw, [Rw +] or Rw, [Rw] or Rw, #data3 1) Rb, [Rw +] or Rb, [Rw] or Rb, #data3 1) bitaddr, bitaddr Rw Rw, #data4 cc_NN, rel bitoff.7 bitoff.7 Rw, #data4 Rw Rw, mem [Rw], mem Rw, #data16 [-Rw], Rw [-Rw], Rb bitaddr, rel cc_C, rel or cc_ULT, rel bitoff.8 bitoff.8 Rw, #data4 Rw Rw, mem mem, [Rw] Rw, #data16 Rw, [Rw+] Rb, [Rw+] bitaddr, rel #trap7 cc, [Rw] cc_NC, rel or cc_UGE, rel bitoff.9 bitoff.9 Rw, #data4 69 2 ANDB 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 BAND DIVL SHR JMPR BCLR BSET OR ORB OR ORB OR ORB OR ORB OR 79 2 ORB 7A 7B 7C 7D 7E 7F 80 81 4 2 2 2 2 2 2 2 BXOR DIVLU SHR JMPR BCLR BSET CMPI1 NEG Semiconductor Group 36 SAB 80C166W/83C166W Hexcode A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 Num- Mnemonic ber of Bytes 2 4 4 4 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 2 2 4 2 2 2 2 2 2 NEGB CMPD1 MOVB DISWDT CMPD1 SRVWDT MOV MOVB JBC CALLI ASHR JMPR BCLR BSET CMPD2 CPLB CMPD2 MOVB EINIT CMPD2 SRST MOV MOVB JNBS CALLR ASHR JMPR BCLR BSET MOVBZ Operands Hexcode C1 C2 C3 C4 Num- Mnemonic ber of Bytes 4 4 MOVBZ MOV Operands Rb Rw, mem [Rw], mem Rw, #data16 Rw, [Rw] Rb, [Rw] bitaddr, rel cc, [Rw] Rw, Rw cc_SGT, rel bitoff.10 bitoff.10 Rw, #data4 Rb Rw, mem mem, [Rw] Rw, #data16 [Rw], Rw [Rw], Rb bitaddr, rel rel Rw, #data4 cc_SLE, rel bitoff.11 bitoff.11 Rw, Rb reg, mem [Rw + #data16], Rw mem, reg reg, #data16 [Rw], [Rw] [Rw], [Rw] cc, addr C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF 4 4 2 2 4 2 2 2 2 2 2 4 4 4 4 2 2 4 2 2 2 2 MOVBZ SCXT MOV MOVB CALLA RET NOP JMPR BCLR BSET MOVBS MOVBS MOV MOVBS SCXT MOV MOVB CALLS RETS JMPR BCLR BSET cc_SLT, rel bitoff.12 bitoff.12 Rw, Rb reg, mem reg, mem mem, reg reg, mem [Rw+], [Rw] [Rw+], [Rw] seg, caddr cc_SGE, rel bitoff.13 bitoff.13 Semiconductor Group 37 SAB 80C166W/83C166W Hexcode E0 E1 E2 E3 E4 Num- Mnemonic ber of Bytes 2 2 4 4 MOV MOVB PCALL MOVB Operands Hexcode FE FF Num- Mnemonic ber of Bytes 2 2 BCLR BSET Operands Rw, #data4 Rb, #data4 reg, caddr [Rw + #data16], Rb reg, #data16 reg, #data8 [Rw], [Rw+] [Rw], [Rw+] cc, caddr reg reg cc_UGT, rel bitoff.14 bitoff.14 Rw, Rw Rb, Rb reg, mem reg, mem Rb, [Rw + #data16] mem, reg mem, reg seg, caddr reg cc_ULE, rel bitoff.15 bitoff.15 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD 4 4 2 2 4 2 2 2 2 2 2 2 4 4 4 4 4 4 2 2 2 MOV MOVB MOV MOVB JMPA RETP PUSH JMPR BCLR BSET MOV MOVB MOV MOVB MOVB MOV MOVB JMPS RETI POP JMPR Semiconductor Group 38 SAB 80C166W/83C166W Notes 1) These instructions are encoded by means of additional bits in the operand field of the instruction x0H - x7H: x8H - xBH: xCH - xFH: Rw, #data3 Rw, [Rw] Rw, [Rw +] or or or Rb, #data3 Rb, [Rw] Rb, [Rw +] For these instructions only the lowest four GPRs, R0 to R3, can be used as indirect address pointers. Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode. Two mnemonic representation alternatives exist for some of the condition codes. Notes on the BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode. The operand `bitoff.n' (n = 0 to 15) refers to a particular bit within a bit-addressable word. Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by `----' is decoded by the CPU. Semiconductor Group 39 SAB 80C166W/83C166W Special Function Registers Overview The following table lists all SFRs which are implemented in the SAB 80C166W/83C166W in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Special Function Registers Overview Name ADCIC ADCON ADDAT ADDRSEL1 ADEIC Physical 8-Bit Description Address Address b FF98H b FFA0H FEA0H FE18H b FF9AH CCH D0H 50H 0CH CDH 8AH 25H 40H BCH 41H BDH 42H BEH 43H BFH 44H C0H 45H C1H 46H C2H 47H A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register Address Select Register 1 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 1 GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H BUSCON1 b FF14H CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 FE4AH FE80H b FF78H FE82H b FF7AH FE84H b FF7CH FE86H b FF7EH FE88H b FF80H FE8AH b FF82H FE8CH b FF84H FE8EH Semiconductor Group 40 SAB 80C166W/83C166W Special Function Registers Overview (cont'd) Name CC7IC CC8 CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CCM0 CCM1 CCM2 CCM3 CP CRIC CSP DP0 DP1 DP2 DP3 DP4 Physical 8-Bit Description Address Address b FF86H FE90H b FF88H FE92H b FF8AH FE94H b FF8CH FE96H b FF8EH FE98H b FF90H FE9AH b FF92H FE9CH b FF94H FE9EH b FF96H b FF52H b FF54H b FF56H b FF58H FE10H b FF6AH FE08H b FF02H b FF06H b FFC2H b FFC6H b FF0AH C3H 48H C4H 49H C5H 4AH C6H 4BH C7H 4CH C8H 4DH C9H 4EH CAH 4FH CBH A9H AAH ABH ACH 08H B5H 04H 81H 83H E1H E3H 85H CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (2 bits, read only) Port 0 Direction Control Register Port 1 Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register (2 bits) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H 0000H 0000H 0000H 0000H 0000H 0000H 00H Semiconductor Group 41 SAB 80C166W/83C166W Special Function Registers Overview (cont'd) Name DPP0 DPP1 DPP2 DPP3 MDC MDH MDL ONES P0 P1 P2 P3 P4 P5 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW S0BG S0CON S0EIC S0RBUF Physical 8-Bit Description Address Address FE00H FE02H FE04H FE06H b FF0EH FE0CH FE0EH FF1EH b FF00H b FF04H b FFC0H b FFC4H b FFC8H b FFA2H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H FEB4H b FFB0H b FF70H FEB2H 00H 01H 02H 03H 87H 06H 07H 8FH 80H 82H E0H E2H E4H D1H 60H 61H 62H 63H 64H 65H 66H 67H 88H 5AH D8H B8H 59H CPU Data Page Pointer 0 Register (4 bits) CPU Data Page Pointer 1 Register (4 bits) CPU Data Page Pointer 2 Register (4 bits) CPU Data Page Pointer 3 Register (4 bits) CPU Multiply / Divide Control Register CPU Multiply / Divide Register - High Word CPU Multiply / Divide Register - Low Word Constant Value 1's Register (read only) Port 0 Register Port 1 Register Port 2 Register Port 3 Register Port 4 Register (2 bits) Port 5 Register (read only) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Reset Value 0000H 0001H 0002H 0003H 0000H 0000H 0000H FFFFH 0000H 0000H 0000H 0000H 00H XXXXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH Semiconductor Group 42 SAB 80C166W/83C166W Special Function Registers Overview (cont'd) Name S0RIC S0TBUF S0TIC S1BG S1CON S1EIC S1RBUF S1RIC S1TBUF S1TIC SP STKOV STKUN SYSCON T0 T01CON T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC Physical 8-Bit Description Address Address b FF6EH FEB0H b FF6CH FEBCH b FFB8H b FF76H FEBAH b FF74H FEB8H b FF72H FE12H FE14H FE16H b FF0CH FE50H b FF50H b FF9CH FE54H FE52H b FF9EH FE56H FE40H b FF40H b FF60H B7H 58H B6H 5EH DCH BBH 5DH BAH 5CH B9H 09H 0AH 0BH 86H 28H A8H CEH 2AH 29H CFH 2BH 20H A0H B0H Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register Serial Channel 1 Baud Rate Generator Reload Register Serial Channel 1 Control Register Serial Channel 1 Error Interrupt Control Register Serial Channel 1 Receive Buffer Register (read only) Serial Channel 1 Receive Interrupt Control Register Serial Channel 1 Transmit Buffer Register (write only) Serial Channel 1 Transmit Interrupt Control Register CPU System Stack Pointer Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register Reset Value 0000H 00H 0000H 0000H 0000H 0000H XXH 0000H 00H 0000H FC00H FA00H FC00H 0xx0H*) 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Semiconductor Group 43 SAB 80C166W/83C166W Special Function Registers Overview (cont'd) Name T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT WDTCON ZEROS Physical 8-Bit Description Address Address FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H b FFACH FEAEH FFAEH b FF1CH 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H B4H D6H 57H D7H 8EH GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H *) The system configuration is selected during reset. Semiconductor Group 44 SAB 80C166W/83C166W Absolute Maximum Ratings Ambient temperature under bias (TA): SAB 83C166W-5M, SAB 80C166W-M ........................................................................... 0 to + 70 C SAB 83C166W-5M-T3, SAB 80C166W-M-T3 ........................................................... - 40 to + 85 C SAB 83C166W-5M-T4, SAB 80C166W-M-T4 .........................................................- 40 to + 110 C Storage temperature (Tstg) ....................................................................................... - 65 to + 150 C Voltage on VCC pins with respect to ground (VSS) ..................................................... - 0.5 to + 6.5 V Voltage on any pin with respect to ground (VSS) .................................................- 0.5 to VCC + 0.5 V Input current on any pin during overload condition .................................................. - 10 to + 10 mA Absolute sum of all input currents during overload condition ............................................. |100 mA| Power dissipation........................................................................................................................ 1 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the voltage on pins with respect to ground (VSS) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the SAB 80C166W/ 83C166W and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the SAB 80C166W/83C166W will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the SAB 80C166W/83C166W. Semiconductor Group 45 SAB 80C166W/83C166W DC Characteristics VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Output low voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) Input leakage current RSTIN pullup resistor Read inactive current Read active current ALE inactive current ALE active current 5) 5) 5) 5) 1) Symbol min. Limit Values max. 0.2 VCC - 0.1 Unit V V V V V Test Condition - - - - VIL VIH SR - 0.5 SR 0.2 VCC + 0.9 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC VOL CC - IOL = 2.4 mA VOL1 CC - VOH CC 0.9 VCC 2.4 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VCC - VOH1 CC 0.9 VCC 2.4 - 1 150 - 40 - 150 - 20 10 50 + 5 x fCPU 30 + 1.5 x fCPU 50 V V A k A A A A A pF mA mA A IOZ IRH IRL 3) 4) CC - - - 500 3) 4) RRST CC 50 VOUT = VOHmin VOUT = VOLmax VOUT = VOLmax VOUT = VOHmin 0 V < VIN < VCC IALEL IALEH IIL - 2100 XTAL1 input current Pin capacitance 6) (digital inputs/outputs) Power supply current Idle mode supply current Power-down mode supply current CC - CIO CC - ICC IID IPD - - - f = 1 MHz TA = 25 C Reset active fCPU in [MHz] 7) fCPU in [MHz] 7) VCC = 5.5 V 8) Semiconductor Group 46 SAB 80C166W/83C166W Notes 1) 3) 4) 5) 6) 7) This specification does not apply to the analog input (Port 5.x) which is currently converted. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold-mode. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at 20 MHz CPU clock with all outputs open. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. A voltage of VCC 2.5 V is sufficient to retain the content of the internal RAM during power down mode. 8) Figure 8 Supply/Idle Current as a Function of Operating Frequency Semiconductor Group 47 SAB 80C166W/83C166W A/D Converter Characteristics VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 4.0 V VAREF VCC + 0.1 V; VSS - 0.1 V VAGND VSS + 0.2 V Parameter Analog input voltage range Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source Symbol Limit Values min. max. Unit V Test Condition 1) 2) 5) 3) 5) VAIN SR VAGND tS tC CC - CC - VAREF 2 tSC 10 tCC + tS + 4TCL 2 TUE CC - RAREF CC - RASRC CC - LSB k k tCC / 250 - 0.25 VAREF = VCC VAGND = VSS tCC in [ns] 4) tS in [ns] 4) tS / 500 - 0.25 Notes 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitors to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. The value for the sample clock is tSC = TCL x 32. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. The value for the conversion clock is tCC = TCL x 32. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the respective current source must allow the capacitors to reach their final voltage level within the indicated time. The maximum internal resistance results from the CPU clock period. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 2) 3) 4) 5) Semiconductor Group 48 SAB 80C166W/83C166W Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic `1' and 0.4 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 9 Input Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 10 Float Waveforms Memory Cycle Variables The timing tables below use three variables which are derived from registers SYSCON and BUSCON1 and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values tA tC tF TCL x Semiconductor Group 49 SAB 80C166W/83C166W AC Characteristics External Clock Drive XTAL1 VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle TCLP SR 62.5 max. 62.5 - - 10 10 0.6 37.5 50 25 25 - - 25 / TCLP TCLP x DCmin Variable CPU Clock 1/TCLP = 1 to 20 MHz min. max. 1000 TCLP-tCLL TCLP-tCLH 10 10 1 - 25 / TCLP TCLP x DCmax ns ns ns ns ns ns Unit tCLH SR 25 tCLL SR 25 tR tF DC TCL SR - SR - SR 0.4 25 Note: In order to run the SAB 80C166W/83C166W at a CPU clock of 20 MHz the duty cycle of the oscillator clock must be 0.5, ie. the relation between the oscillator high and low phases must be 1:1. So the variation of the duty cycle of the oscillator clock limits the maximum operating speed of the device. The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. Figure 11 External Clock Drive XTAL1 Semiconductor Group 50 SAB 80C166W/83C166W AC Characteristics (cont'd) Multiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to +110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 6 TCL (150 ns at 20-MHz CPU clock) Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge max. - - - - - 5 42.5 - - 47.5 + tC 72.5 + tC 72.5 + tA + tC 100 + 2tA + tC - Variable CPU Clock 1/TCLP = 1 to 20 MHz min. TCLmin - 10 + tA TCLmin - 15 + tA TCLmin - 10 + tA TCLmin - 10 + tA -10 + tA - - TCLP - 10 + tC TCLP + TCLmin - 10 + tC - - - - 0 max. - - - - - 5 TCLmax + 5 - - TCLP - 20 + tC TCLP + TCLmin - 20 + tC TCLP + TCLmin - 20 + tC 2TCLP - 25 + 2tA + tC - ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 CC 15 + tA CC 10 + tA CC 15 + tA CC 15 + tA CC -10 + tA CC - CC - CC 52.5 + tC CC 77.5 + tC SR - SR - SR - SR - SR 0 Semiconductor Group 51 SAB 80C166W/83C166W Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. 47.5 + tF - - - - Variable CPU Clock 1/TCLP = 1 to 20 MHz min. - TCLP - 15 + tC TCLP - 15 + tF TCLP - 15 + tF TCLP - 15 + tF max. TCLP - 15 + tF - - - - Unit Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR t19 t22 t23 t25 t27 SR - CC 47.5 + tC CC 47.5 + tF CC 47.5 + tF CC 47.5 + tF ns ns ns ns ns Semiconductor Group 52 SAB 80C166W/83C166W t5 ALE t16 t25 A17-A16 (A15-A8) BHE t17 Address t27 t6 t7 t19 Read Cycle BUS Address t18 Data In t8 RD t10 t14 t12 Write Cycle BUS Address t23 Data Out t8 WR t10 t22 t12 Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 53 SAB 80C166W/83C166W t5 ALE t16 t25 A17-A16 (A15-A8) BHE t17 Address t27 t6 t7 t19 t18 Address Data In Read Cycle BUS t8 RD t10 t14 t12 Write Cycle BUS Address Data Out t23 t8 WR t10 t22 t12 Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 54 SAB 80C166W/83C166W t5 ALE t16 t25 A17-A16 (A15-A8) BHE t17 Address t27 t6 t7 t19 Read Cycle BUS Address t18 Data In t9 RD t11 t15 t13 Write Cycle BUS Address t23 Data Out t9 WR t11 t22 t13 Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 55 SAB 80C166W/83C166W t5 ALE t16 t25 A17-A16 (A15-A8) BHE t17 Address t27 t6 t7 t19 Read Cycle BUS Address t18 Data In t9 RD t11 t15 t13 Write Cycle BUS Address Data Out t23 t9 WR t11 t13 t22 Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 56 SAB 80C166W/83C166W AC Characteristics (cont'd) Demultiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF ALE cycle time = 4 TCL (100 ns at 20-MHz CPU clock) Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay) Data float after RD rising edge (no RW-delay) Data valid to WR max. - - - - - - 47.5 + tC 72.5 + tC 72.5 + tA + tC 100 + 2 tA + tC - 47.5 + tF 15 + tF - Variable CPU Clock 1/TCLP = 1 to 20 MHz min. TCLmin - 10 + tA TCLmin - 15 + tA TCLmin - 10 + tA -10 + tA TCLP - 10 + tC max. - - - - - ns ns ns ns ns ns ns Unit t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 CC 15 + tA CC 10 + tA CC 15 + tA CC -10 + tA CC 52.5 + tC CC 77.5 + tC SR - SR - SR - SR - SR 0 SR - SR - CC 47.5 + tC TCLP+TCLmin - - 10 + tC - - - - 0 - - TCLP - 15 + tC TCLP - 20 + tC TCLP+TCLmin ns - 20 + tC TCLP+TCLmin ns - 20 + tA + tC 2TCLP - 25 + 2tA + tC - TCLP - 15 + tF TCLmin - 10 + tF - ns ns ns ns ns Semiconductor Group 57 SAB 80C166W/83C166W Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. - - - Variable CPU Clock 1/TCLP = 1 to 20 MHz min. TCLmin - 10 + tF -10 + tF 0 + tF max. - - - Unit Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR t24 t26 t28 CC 15 + tF CC -10 + tF CC 0 + tF ns ns ns Semiconductor Group 58 SAB 80C166W/83C166W t5 ALE t16 t26 A17-A16 A15-A0 BHE t17 Address t28 t6 t20 t18 Data In Read Cycle BUS (D15-D8) D7-D0 t8 RD t14 t12 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t8 WR t22 t12 Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 59 SAB 80C166W/83C166W t5 ALE t16 t26 A17-A16 A15-A0 BHE t17 Address t28 t6 t20 t18 Data In Read Cycle BUS (D15-D8) D7-D0 t8 RD t14 t12 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t8 WR t22 t12 Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 60 SAB 80C166W/83C166W t5 ALE t16 t26 A17-A16 A15-A0 BHE t17 Address t28 t6 t21 t18 Data In Read Cycle BUS (D15-D8) D7-D0 t9 RD t15 t13 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t9 WR t22 t13 Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 61 SAB 80C166W/83C166W t5 ALE t16 t26 A17-A16 A15-A0 BHE t17 Address t28 t6 t21 t18 Data In Read Cycle BUS (D15-D8) D7-D0 t9 RD t15 t13 Write Cycle BUS (D15-D8) D7-D0 t24 Data Out t9 WR t22 t13 Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 62 SAB 80C166W/83C166W AC Characteristics (cont'd) CLKOUT and READY VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 62.5 - - 5 5 10 + tA - - - - - 0 + 2tA + tF 2) Variable CPU Clock 1/TCLP = 1 to 20 MHz min. TCLP TCLmin - 10 TCLmin - 10 - - 0 + tA 10 10 TCLP + 15 20 0 0 max. TCLP - - 5 5 10 + tA - - - - - TCL - 25 + 2tA + tF 2) Unit t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC 62.5 CC 15 CC 15 CC - CC - CC 0 + tA SR 10 SR 10 SR 77.5 SR 20 SR 0 SR 0 ns ns ns ns ns ns ns ns ns ns ns ns Notes 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. 2) Semiconductor Group 63 SAB 80C166W/83C166W Running cycle 1) READY waitstate MUX/Tristate 6) CLKOUT t32 t30 t34 t33 t31 t29 7) ALE Command RD, WR 2) t35 Sync READY 3) t36 t35 3) t36 t58 Async READY 3) t59 t58 3) 5) t59 t60 4) t37 see 6) Figure 14 CLKOUT and READY Notes 1) 2) 3) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here. 4) 5) 6) 7) Semiconductor Group 64 SAB 80C166W/83C166W AC Characteristics (cont'd) External Bus Arbitration VCC = 5 V 10 %; VSS = 0 V TA = 0 to + 70 C for SAB 83C166W-5M, SAB 80C166W/83C166W-M TA = - 40 to + 85 C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3 TA = - 40 to + 110 C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4 CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF Parameter Symbol CPU Clock = 16 MHz Duty cycle 0.4 to 0.6 min. max. - 50 60 25 60 20 - - - - Variable CPU Clock 1/TCLP = 1 to 20 MHz min. max. - 50 60 25 60 Unit HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay Other signals release Other signals drive t61 t62 t63 t66 t67 SR 20 CC - CC - CC - CC - ns ns ns ns ns Semiconductor Group 65 SAB 80C166W/83C166W CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t66 Other Signals 1) Figure 15 External Bus Arbitration, Releasing the Bus Notes 1) 2) The SAB 80C166W/83C166W will complete the currently running bus cycle before granting bus access. This is the first possibility for BREQ to get active. Semiconductor Group 66 SAB 80C166W/83C166W 2) CLKOUT t61 HOLD t62 HLDA t62 BREQ t62 1) t63 t67 Other Signals Figure 16 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the SAB 80C166W/83C166W requesting the bus. The next SAB 80C166W/83C166W driven bus cycle may start here. 2) Semiconductor Group 67 |
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